Intel CPUs, an overview

by Peter Perlsø,
published 17/11 - 2002,
updated October 2006, and 30th Aug 2009
based on a draft from Feb 1995

The purpose of this article is to create an easily accessible and readable reference to the chronology of Intel CPU lines.

This is a work in progress, and will be updated when time allows. Corrections/additions welcome.

Pre-32 bit CPUs

CPU (codename) year clock (MHz) transistor count process (µ) & die size comments    
4004 15. Nov. 1971 108 KHz 2300 10 µ (12 mm^2) 4 bit bus, 640 byte address range    
8008 1. April 1972 200 KHz 3500 " 8 bit bus, can address 16 KB of memory    
8080 1. April 1974 2 MHz 6000 6 µ 10x performance of 8008, 64 KB address range    
8086 June 8. 1978 4.77 - 8 - 10 MHz 29 000 3 µ 5 MIPS, 1 M RAM adressable, 16 bit data bus, 360$    
8088 1. June 1979 4.77 MHz 29 000 " essentially an 8086 with a 8 bit data bus. Used in IBM's original PC (1981)    
80286 1. Feburary 1982 6 - 12.5 MHz 134 000 1.5 µ first x86 protected mode CPU, 25 MIPS, 16 bit data bus, 16 M RAM adressable, virtual memory functionality, 360$, used in IBM's PC AT (1984)    

i386 architecture CPUs

CPU (codename) year clock (MHz) transistor count process (µ) & die size comments
80386 - first i386 architecture chip (32 bit integer registers)
SX June 1988 16 - 25 275 000 1 µ Single word eXternal bus (16 bit), 24 bit address bus (16M RAM addressable) 50 MIPS
DX (P9) 17. October 1985 16 - 33 275 000 1 µ 4 GB address range, Double word eXternal bus (32 bit), 32 bit address bus (4G RAM addressable) 299$, first used in Compaq Deskpro 386/16 (1986)
80486 - Pipelined Integer unit, internal FPU
486 SX 22. April 1991 16 - 33 1.185 M 1 µ internal FPU disconnected
486 DX (P4) 10. April 1989 25 - 50 1.2 M 1 - .8 µ L1 cache on chip, 900$
486 DX2 March 1992 50 - 66     Double clocked DX
486 DX4 March 1994 75 - 120     Triple clocked DX, larger L1 caches

Pentium class CPUs

Pentium / P5 - Superscalar CPU, Pipelined FPU, writeback MESI data cache, Dynamic Branch Prediction, Socket 7, 64 bit data bus
P5 22. March 1993 60 - 66 3.1 M .8 µ 878$, 8+8 K L1
P5 ? 31. May 1995 ? 75 - 90   .6 µ 3.3 V
P54C/CS Feb 1996 - ? 100 - 200 3.3 M 0.35 µ ?  
P55C (MMX) 1996 - 97 ? 166 - 266 MHz 3.1/3.5? M .35 µ ?, 15,7 W Integer SIMD, 16+16 K L1

Pentium Pro cores

Pentium Pro / P6 - Superscalar OOO, RISC core, Dual Independent Bus, on-chip L2 cache
P6 11. January 1995 - 96 150 (2H 1995), 166 ($1319), 180, 200 ($1528) MHz 5.5 M (L2 cache: 15.5 or 31 M) 0.6 (150) - 0.35 (166 - 200) µ BiCMOS (196 - 306 mm^2) 256, 512 K L2 @ CPU, Socket 8, 2x 8 K L1, 64 GB addressable, 14-20 W, 66 MHz FSB
Pentium II / P2 - P6 w/ MMX (SIMD), 66 / 100 MHz FSB
Klamath 7. May 1997 233, 266, 300 MHz 7.5 M 0.35 µ 512 K L2 @ 1/2 CPU, Slot 1, FSB @ 66 Mhz, 2.8 V core, 2x 16 K L1, segment registers for 16-bit apps, 34-43 W
Deschutes Jan - 15. April 1998 333 Mhz (FSB @ 66) 350 - 450 MHz (FSB @ 100) " 0.25 µ 512 K L2 @ 1/2 CPU, Slot 1, 2.0 V core, 24 - W
Celeron (Covington) 15. April 1998 266 - 300 MHz, FSB @ 66 7.5 M   Deschutes w/ no L2, Slot 1
Celeron A (Mendochino) 4. Jan, 1999 - 300 - 500 Mhz, Slot 1 & s370 - (366 - 400: 4. January, 433: 21. March, 466: 26. April, 500: 1. August) 19 M   128 K L2 @ CPU (ondie), s370
P2 Mobile (Dixon) 2H 98 266-366 MHz     256 K L2
Xeon (Drake) 29. June, 1998 400 - 450 MHz, FSB @ 100 7.5 M .25 µ .5 , 1, 2 M L2 @ CPU, Slot 2
Pentium !!! / P3 - SSE / KNI / MMX-2 (FP SIMD), Serial#
Katmai mid 1999 450 - 600 MHz, FSB @ 100 9.5 M .25 µ (106 mm^2) 512 K L2 @ 1/2 CPU connected by a 64 bit bus, Slot 1, 16 + 16 K L1
Pentium III B 27 Sept 99 533 - 600 MHz, FSB @ 133 " .25 µ "
Pentium III E (Coppermine) 25 Oct 99 600 MHz - 1.2 GHz, 100 - 133 (EB) MHz FSB 28.1 M w/ cache .18 µ 256 K L2 Advanced Transfer Cache (ATC) @ CPU (on die) with a 256 bit L2 bus, s370, 1.65 V core, Advanced System Buffering
Tualatin 30. July 2001 - 02 866 MHz - 1.133 - 1.4 GHz, 133 MHz FSB   .13 µ 512 K L2 @ CPU, s370
Coppermine-128 (Celeron) late 2000 - 02 667 - 766 Mhz (FSB@66), 800 MHz - 1.1 GHz (FSB@100) 28 M ? .18 µ 128 K L2 @ CPU, s370, 1.5 V core
Celeron Tualatin 2002 1 - 1.4 GHz, 100 MHz FSB " ? .13 µ 256 K L2 @ CPU
PIII Xeon (Tanner) 17. March 1999 500 - 550 MHz (550: 23. August), FSB @ 100   .25 µ ? .5, 1, 2 M L2 @ CPU, Slot 2
Pentium III Xeon E (Cascades) 25. October 99 600, 667, 733 MHz, 800 MHz (mid 2000), FSB @ 133   .18 µ 256 K L2 @ CPU

Pentium 4 cores

Pentium 4 / PIV - NetBurst architecture: SSE-2 (DP FP SIMD), Instruction Trace Cache, Hyperpipelined (20 stages), Quad-pumped FSB (400+ MHz), smaller L1 caches (12 kuops I + 8 K D)
(Willamette, P68) June 2000 1.3 - 2 GHz 42 M w/ cache   256 K L2, s423,
Pentium4-A (Northwood) 2001 Q4 1.8 - 2.6 GHz 55 M ? w/cache .13 µ 512 K L2, s478
Pentium4-B - (Northwood A) 2002 - 03 533 FSB, 2.266 - 2.8 - 3.06+ GHz (HT: ≥ 3.06 GHz) 55 M " "
Pentium4-C April 2003 800 FSB, HT, 2.4 - 3 GHz 55 M " " , released as a companium to the Canterwood chipset
Pentium4-D - (Prescott)* 2004 ? up to 5.2 GHz, FSB 1066 MHz   .09 µ " + 1 M L2, SSE3 (= PNI / Prescott New Instructions)
Celeron May 2002 1.6 - 2.8 GHz, FSB @ 400 MHz 55 M ?   128 K L2, s478
Xeon (Foster) Mar 2001 1.4, 1.5, 1.7, 2.0 GHz, FSB @ 400 Mhz 30 M (core), 108 M w/ cache   256 K L2, s603,2-way MP
Xeon MP (Foster MP) Mar 2001 1.4, 1.5, 1.6 GHz     Foster + 512 K / 1 M (1.6 GHz only) L3 on-die, HT,≥4-way MP
Xeon Northwood (Prestonia) Feb 2002 1.8 - 2.8 GHz (533 FSB, 2.0 - 2.8 GHz since Nov 2002)   .13 µ Foster + 512 K L2, HT, 2-way MP, Plumas chipset
Xeon MP Northwood (Gallatin) Nov 2002 1.5, 1.9, 2.0 GHz   .13 µ Prestonia + 1 / 2 M (2 GHz only) L3, ≥4-way MP
Xeon (Nocona)* 2003 4 GHz, FSB @ 667 MHz   .9 µ  
Pentium4-E - (Tejas)* 2005 FSB @ 1.2 GHz   .9 µ  
(Nehalem)* 2005 9.2 - 10.2 GHz, FSB @ 1.5 GHz   .9 µ 10 GHz? yeah right
Pentium 5 / D          
           

 

 

Pentium M nnn class CPUs

Pentium M / Centrino?
Pentium M 320 - 360 March 2003 1.3 GHz # transistors nm process Banias, Dothan, Yonah: "Centrino" chipset core component
           
725   1.6 GHz, FSB@400     s478, 8 K L1, 2 M L2
730   1.6, FSB@533     "
735   1.7, FSB@400     "
740   1.73, FSB@533     "
745   1.8, FSB@400     32 K L1
           
750   1.86 GHz, FSB@533     s479 FCBGA, 32 K L1, 2 M L2
755   2, FSB@400     "
760   2, FSB@533     "
765   2.1, FSB@400     "
770   2.133, FSB@533     "
           
           
Celeron M   1.2, 1.3, 1.4, 1.5GHz     512 KB L2, s479 , FSB@400
Celeron M 360 - 390   1.4 - 1.7 GHz     1 M L2, s479, 64 KB L1
Celeron M 410 - 450   1.46 - 2.0 GHz     1 M L2, FSB@533, s479
           

 

Pentium 4 nnn class CPUs

Pentium 4 nnn - NetBurst architecture: SSE-3 (PNI / Prescott New Instructions), Instruction Trace Cache, Hyperpipelined (20 stages), Quad-pumped FSB (533+ MHz), larger L1 caches (12 kuops I + 16K D), HyperThreading
Celeron D 315 - 320 2004 2.26 GHz - 2.40 GHz     FSB@533 MHz , s478
325 - 345, J   2.53 - 3.0 GHz     s478, or: J = s775
           
Pentium 4 505   2.66 GHz     FSB@533 MHz, s775, 1 M L2
Pentium 4 520 - 570   2.8 - 3.8 GHz     FSB@800 MHz , s775, 1 M L2
Pentium 4 630 - 670   3 - 3.8 GHz     FSB@800 MHz, s775, 2 M L2
Pentium D 820 - 840 Q2 2005 2.8 - 3.2 GHz     'D': Smithfield Dual Core CPUs, 1 MB L2 per core (2 M L2 total)
Pentium D 915 - 960   2.8 - 3.6 GHz     FSB@800, 4 M L2 (2 M per core), s775
Pentium D 955, 965 EE   3.46, 3.73 GHz     FSB@1066 MHz

 

Intel "Core" Series

Core series - XD bit (eXecute Disable)
Core Solo Q1 2006 single core , 1.5 - 1.66 GHz   65 nm  
"Yonah" - Core Duo Q1 2006 dual core , 1.66 - 2.16 GHz   65 nm process 32 bit, FSB @ 667 MHz , 2 MB shared L2 cache
"Merom" - Core 2 Duo Q2 2006 2.5 GHz +, dual core   65 nm process 64 bit, short pipeline, for portables (low power consumption), FSB @ 1066 MHz, 2 MB shared L2, includes LaGrande Technology, Vanderpool Technology, and Clackamas Technology (64-bit extensions)
"Conroe" - Core 2 Duo Q3 2006     " desktop variant of Merom, 2x2 MB L2, candidate for Apple-used desktop CPU, FSB @ 1066 MHz
"Woodcrest" - Xeon Q3 2006 2.0 - 2.66 - 3.0 GHz   " server variant of Conroe, 1333 MHz FSB
"Cloverton"       " Dual Woodcrest chip w/ FSB @ 533 MHz (?)
           

 

IA-64 class CPUs

IA-64 - EPIC architecture: VLIW core, Branch prediCAtion, huge register files, Slot M
Itanium (Merced / P7) June 2000 733 (2M L3) - 800 (4M L3) MHz,100 MHz FSB   180 nm 96 K L2, 2 - 4 M L3
Itanium 2 (McKinley) 2002 0.9 - 1 GHz, 400 MHz FSB 28 M w/o cache, 221 M 180 nm (~420 mm^2) 256 K L2, 1.5 - 3 M on-die L3
Madison* 2003 1.2 - 1.5 GHz 410 M w/ cache 130 nm 4-6 M on-die L3
Deerfield* 2003     130 nm 1 M on-die L3 (low-cost/desktop IA-64)
Montecito* 2004 1.6 - 1.8 Ghz   90 nm dual core, 9-12 M L3
Chivano* 2005 2.0 - 2.2 GHz   90 nm dual core, 8 M on-die L3
Tanglewood?          

 

nnn codes and their corresponding CPU frequencies

Pentium 4 nnn:

505 - 2.66 GHz (FSB@533)
520 - 2,8 GHz (FSB@800)
530 - 3, 540 - 3.2, 550 - 3.4, 560 - 3.6, 570 - 3.8

2 M L2 cache:

630 - 3 GHz, 640 - 3.2, 650 - 3.4, 660 - 3.6

Pentium M nnn:

320 - 1.3 GHz
360 - 1.4

725 - 770 : see table

Celeron M nnn:

360 - 1.4 GHz, 370 - 1.5, 380 - 1.6, 390 - 1.7

533 MHz FSB:

410 - 1.46 GHz, 420 - 1.6, 430 - 1.73, 440 - 1.86, 450 - 2

Celeron D nnn:

 315 - 2.26 GHz, 320 - 2.40; 325, J - 2.53; 330, J - 2.66; 335, J - 2.80; 340, J - 2.93; 345, J - 3.0

(note: 'J' denotes a Socket 775 CPU)

Pentium 4 nnn:

1 M L2 cache:

505 - 2.66 GHz, 520 - 2.8, 530 - 3, 540 - 3.2, 550 - 3.4, 560 - 3.6, 570 - 3.8

2 M L2 cache:

630 - 3 GHz, 640 - 3.2, 650 - 3.4, 660 - 3.6, 670 - 3.8

Pentium 4 D:

820 - 2.8 GHz
830 - 3.0
840 - 3.2

 

Notes: sXXX = Socket XXX, HT = HyperThreading, nm = nanometer (1/1000 micron/µ), * = rumored

Sources: Intel, and other various web pages. Thanks to the guys @ Aces Hardware Tech Board, comp.sys.intel and newz.dk.


Other references:

• Wikipedia / List of Intel Microoprocessors
• Wikipedia / List of Intel chipsets

 


cc, 2002 - 2009, Peter Bjørn Perlsø, titancity.com