by Peter Perlsø,
published August 2001/March 2002,
updated October 2006 and 30. August 2009
Foreword: The PowerPC, or PPC for short, is a CPU Instruction Set Architecture jointly developed by the AIM (Apple-IBM-Motorola) Consortium back in the early 90's. It has been driving Apple's PowerMac line and advanced Amiga computers since 1994, and has been extensively used in embedded devices as well. This article gives a brief presentation of the current span of the PPC family.
Additions and corrections are welcome.
| CPU & codename | Year | MHz | power (W) | IU | FPU | L1 (K) | L2 (M) | L3 (M) | process (µ) | die size (mm^2) | transistors (M) | FSB (MHz) | ||
| G1 601 | 93 | 60 - 100 | 2 | sp | 32 u | - | - | .6 | 2.8 | 33-50 | ||||
| 601+ | 94? | 110 | .5 | ? 81 | 2.8 | |||||||||
| G2 603 | 95 | 75 | 1 | sp | 8+8 | .5 | 1.6 | 37.5 | ||||||
| 603e - Stretch (100), Valiant (166) | 96 | 100 - 166 | 3 | 16+16 | .5, .35 | 81,98 ? | 2.6 | 33+ | ||||||
| 603ev - Slant Six (200), Goldeneye? | 97 | 180 - 300 | 4-6 @300 | .35, .29 | 36,42? | 2.6 | 40 - 60 | |||||||
| 604 | 95 | 120 - 150 ? | 16.5 | 3 | dp | 16+16 | .5 | 196 | 3.6 | 40 - 50 | ||||
| 604e - Sirocco | 96 | 166 - 200 (?) | 10-15 | 32+32 | .5 ? | 148 | 5.1 (more L1 cache) | 40+ | ||||||
| 604ev | 96 | 180 - 233 | .35 | 96 | 5.1 | 40+ | ||||||||
| 604ev - Mach 5 | June 97 | 250 - 350 | .25 | 47 | 5.1 | 50 | ||||||||
| G3 750, 755 - Arthur, Lone Star, Conan | 97 | 233 - 400 | 5.7 - 8 | 2 | sp | 32+32 | .25, .5, 1 | - | .29 - .22 | 67,40 | 6.35 w/o L2 | 66, 755: 100 | ||
| 740, 745 | 200 - 333, 350 | - | - | .29, .25 (>266), .22 (>300) | 67,51 | 66, 745: 100 | ||||||||
| 750CX SideWinder , 750CXe Anaconda | SideWinder: 2000, Anaconda: early 2001 | 366 - 600 | .25 OD, 2-way SA | - | .18 | 42.7 | 21.5 w/ L2 | Anaconda: 133 | ||||||
| 750FX / 770 - Sahara | 2002 | 600 - 900 MHz | .5 OD, 2-way SA | - | .13 Cu SOI | 36.6 | 29 | 100 | ||||||
| 750GX - Gobi | 2003 | > 733 MHz - 1.1 GHz | 1 OD, 4-way SA | - | .13 Cu SOI | 51.9 | 44 ? | 133 | ||||||
| G4 7400 - Typhoon, Max | 99 | 350 - 450 (problems with 500 MHz parts) | 8 @ 400 | 2 | dp | 32+32 | .5, 1, 2 | - | .25, HiP5 | 83 | 10.5 | 100 MB | ||
| 7410 - Nitro, Goldfinger | 2000 | 400 - 550 | - | .18 Cu | 52 | 10.5 | 100 MB | |||||||
| "G4.5" 7450, 7451 - V'ger, G4+ | 533, 667, 733, 867? | 4 | dp | 32+32 | .25 OD | 1, 2 | .18 Cu | 106 | 33 | 133 MB | ||||
| 7455 - Apollo (passed 1 GHz) | late 2000 | 733, 800, 867, 933, 1G GHz | 21.3 @ 1G (max) | 1, 2 | .18 Cu SOI | 106 | 33 | 133 - 167 MB | ||||||
| 7440, 7441 | 550 - 667 | - | .18 Cu | 106 | 33 w/o L2 | 100 - 133 MB | ||||||||
| 7445 | 600 - 1 GHz | - | .18 Cu SOI | 100 - 133 MB | ||||||||||
| 7457/7460 | 2002? | 1 - 1.267 GHz | 15.8 (typ)-22 (max)@1,267 G | 4 | dp | 32+32 | .5 OD | up to 4 | .13 Cu SOI | 58 w/ L2 | 167 MB | |||
| 7447A | 2003 | 1.42 - 1.5 GHz | 18.3 (typ)-26(max) W @ 1,42 G | 4 | dp | 32+32 | .5 OD | - | .13 SOI 9 layer | 133 - 167 MB | ||||
| 7448 (e600 core) | 2004 (?) | 1.5 - 1.67 GHz | 10(typ)-15(max) W @ 1,5 G | 4 | dp | 32+32 | 1 OD, ECC | - | 90 nm SOI | 167 - 200 MB |
| CPU | GHz | IU | FPU | L1 (K) | L2 (M) | process (nm) | transistors (M) | comments |
| 7500/8500 Goldfish | 1 - 1.4 | ? | dp | ? | .5? | 130 | 58 | FSB@400, scrapped |
| IBM 970/G5 | 1.6 - 2.7 | 2 | dp | 64 i + 32 d | .5 OD | 90 | 55 ? | FSB @ .8 - 1 GHz |
| 980 | 4? | 65 nm ? | enhanced 970, 2004 | |||||
| POWER5 (2004) | dual core | |||||||
| 970FX | - 2.5 | .5 OD | 28 ? (core) | 55 W | ||||
| 970FX low power | 1.2 - 1.6 | .5 OD | 16 W @ 1,6 GHz | |||||
| 970MP Antares | 1.4 - 2.5 | 2x 1 OD | aka 970GX, dual core | |||||
OD = (Cache) On Die: speed: 1/1, backside
MB = MaxBus
µ = microns, millionths of a meter
nm = nanometer, 1/1000 of a micron
names in italic denotes unreleased or rumored names/products
The First Generation: The 601 marks the dawn of the PowerPC processor family, anno 1993. It was used in Apple's PowerMac line in April 1994. The 601 is essentially a hybrid of the PowerPC instruction set, and the older IBM POWER ISA.
The Second Generation: The second PPC generation encompasses the 603 and 604 CPU architectures (as well as the stillborn 620). These were both evolutions of the 601 chip, as they dropped POWER ISA support and solely supported the PowerPC ISA. The 604 is a high-performance CPU geared towards use in workstations and multiprocessor installations. The 603 is a lower-performance chip aimed at entry level computers, portables and embedded applications, due to its low power consumption and heat dissipation.
The first 603's small L1 caches became a hindrance to tasks performed on the chip, as the caches could not feed the execution core with data at a sufficient rate. This was corrected in the 603e, which, at 100 MHz, processed data almost twice as fast as its 75 MHz predecessor. Unfortunately, Apple had already shipped a large number of Performas computers based on the 603 chip, and the reputation of this product line suffered greatly, in part because of the shortcomings of the 603.
All 603's use the MEI memory coherency protocol. The 604's use the more efficient MESI protocol, greatly increasing its potential as a multiprocessor CPU. Both shipped late in 1994.
Third Generation: The G3 is a common name for the PPC 750 line of processors. It was coined by Apple Computer when they started using these chips in the Power Macintosh G3 line of computers.
The innovation of the PPC 750 is that it applies a dedicated "backside" bus for communicating with a closely coupled L2 cache (named the "backside cache"), connected to the core by a 64 bit data bus. Apart from reducing system bus congestion, the use of a seperate L2 cache bus allowes the CPU core to retieve instructions and data much faster than the earlier generations of processors, and hence cut computation time down significantly.
IBM's later version of the G3, known as 750CX, CX3, FX and GX, sports a wider (256 bit) L1 cache bus.
Fourth Generation: Announced by Motorola on the 31st of August, 1999, the G4 adds SIMD (Single Instruction, Multiple Data) abilities to the PPC family. Intel added such functionality to their Pentium line in 1997 under the name of MMX. The Motorola counterpart to MMX was codenamed VMX, later dubbed AltiVec (Apple calls it "Velocity Engine"), and adds a new execution unit to the PowerPC core, with 162 associated instructions. This AltiVec unit has a 32-entry, 128-bit wide register file. Code written to take advantage of the AltiVec unit can theoretically perform up to 16 times faster than normal code on older PowerPC CPU's. Additionally, system bus bandwidth is more than doubled due to the implementation of the MaxBus protocol. The PPC 7400 also excels as a multiprocessor chip, as it supportes the MERSI protocol for memory coherency.
Generation 4.5: Although the PPC 7450 is formally a member of the G4 family, I believe that placing it in the former category doesn't do this chip justice, due to many microarchitectural enhancements it contains over the 7400 line. First of all, The 7450 has four Integer Units instead of the predecessor's two. Second, it has 4 independent AltiVec units, compared to the former two. Third, it has much enhanced dispatching capabilities, feeding the execution units much more rapidly. Fourth, it has a 36-bit address bus, allowing a physical address space of 64 gigabytes of memory. Additionally, it employs an on-die L2 cache, running at processor speed, connected the CPU core by a 256 bit wide bus for super-fast cache access.
Generation 5: With the failure of Motorola to produce their G5 chip (which is rumored to have been scrapped by Mot management), Apple has turned to IBM for the PowerPC 970, a 64-bit CPU with AltiVec support. It is based on IBM's POWER 4 chip, and has been announced at WWDC 2003, June 23rd.
Sources: Apple, MacWEEK, Motorola SPS, IBM Microelectronics and others.
NB: All PowerPC CPU's with backside L2 or L3 capability have on-chip cache tags (that means PPC 750 and later, excluding 74X and 744X).
Sources and Further reading:
Freescale PowerPC,
PowerPC,
PowerPC G4,