Graphics Hardware History

* THIS IS A WORK IN PROGRESS! *

by Peter Bjørn Perlsø
created 1st of September 1999 (first draft April 1999)
updated 30th of September 2006, and 30th of August 2009

Additions and corrections are welcome. I will update this article as time allows for it.

The purpose of this article is to give an authoritative representation of the progress in the field of computerized graphics acceleration, primarily 3D.

Related and useful articles:

+ How much bandwidth does the various buses provide?

Definitions:

Fill rate: The (pixel) fill rate is quite simply, how many pixels on the computer display, your graphics hardware can alter (fill with new data) per second. But how much is a mega pixel really in practical terms? Take a look at the graphic below:



If you're looking for a rough estimate of how fast a given gfx card is, look at the texel fill rate and the triangle setup capabilities.

As you can see from the above table, the pixel counts climb into the millions pretty quickly as you increase your display resolution. To determine how high a fill rate you need, you can use this formula:

horizontal resolution * vertical resolution * desired frame rate = target fill rate

So, for example, to play your favorite 3D game in 1600*1200 pixels with 60 frames per second (fps), you'd need a graphics chip that can pump out 1600*1200*60 = 115,2 million pixels per second. By modern graphics hardware, this is easily achieved.

Stencil Buffer: Pixel-based buffer used by graphics accelerators to store effect information for individual pixels. A stencil buffer 8 bit wide would allow for 256 (2^8) effect layers "on top" of each pixel. Usually employed in conjunction with a z buffer for effects such as fogging, shadowing etc.

Z Buffer: Pixel-based depth buffer used to determine the visibility of pixels in a rendered scene. The buffer provides a way for the renderer to determine whether a rendered pixel should be sent to the frame buffer, by comparing z (depth) values for each pixel in the rendered polygons. The smaller the z value for a pixel, the closer it is to the observer. If a rendered pixel has a lower z value than an already rendered pixel, its color information overwrites that if the "old" pixel.

Key to charts:

MP = Mega Pixels, MT = Mega Texels, GP = Giga Pixels , GT = Giga Texels

3Dfx hardware

SPMT = Single Pass MultiTexturing, SPTF = Single Pass Trilinear Filtering, FTS = Full Triangle Setup (offloads CPU)
SLI = Scan Line Interleaving, allows you to combine two gfx cards into one logical card.

VSA-100: 8-bit stencil rendering, and advanced texture and color combine capabilities, DVD hardware assist. DXTC. T-buffer - not on V4 cards, only V5 (full screen antialiasing (FSAA), motion blur, programmable depth-of-field, oft shadows and reflections etc.)

ATI hardware

other hardware

NOTES:

A texture unit is the same (performance wise) as a texel pipeline. You calculate the texel fill rate by multiplying the pixel fill rate by the number of texel/texturing units (TMU's).

Memory bandwidth is calculated by multiplying the memory bus width with the memory clock speed. Keep in mind that this will give you the peak speed (theoretical maximum). Fill rate is calculated by multiplying core clock by the number of pixel and texel pipelines in the chip.

- Rage Pro Turbo is really just a Rage Pro with a nice name. Turbo name was due to a software update that needed extra publicity from ATI, i think.
- RAGE 128 supports textures up to 2048^2 pixels.
- Rage 128 Ultra was a version of the 128 Pro with extra RAM (16 M in all) at a cheap price. Summer 2000?
- Radeon 8500 featured TRUFORM, SMARTSHADER. RADEON 8500LE was later renamed 9100.

Misc.

gfx segments, 2002:
100 $ - mainstream, 200 $ - high end, 300 $ - ultra high end

will be added at a later time :

definitions and explanations of:

texel fill rate, GPU definition, frame buffers, texture memory, bump mapping, bi- & trilinear filtering, FSAA, W-buffers, (vertex) shaders, DVD assist, multitexturing, antialiasing (AA), anisotropic filtering (AF), etc.

Thanks goes to:

Eyal Teler,

This article cc 2003-2009 Peter Bjørn Perlsø, titancity.com